| Make and Makefiles |
» Make and MakefilesPage: 1 of 1
By: Ovidiu
Last updated: 17 April
Make and Makefiles a short tutorial of what are they, and what they do
First of all I want to mention that this tutorial is far from complete
, is just a quick begining for a green programmer.
This article is a about one of the most important tool in development , the
project management with one of the oldest and wide spreaded tool for project
management.This tool is strictly necesarely when you projects grow
bigger and bigger and the time to compile them get longer and longer, and
some times you don't need to compile the whole project because you just made
a small modification in a library ar other program file. Make will let you
compile only the newly modified sources, the only ones that need recompiling.
So let's see how it is done.
Well pretty simple just type:
make
What will happen ? Well you have a file called "makefile" or "Makefile" lots
of stuff will happen if you dont' ... well nothig. That mean you need to
write a "makefile"
GNU dudez recommend to name your makefiles "Makefile" with a big M because
is easier to seen them from the multitude of sources. Well just listen to
them because they are old and rusted and they know what they talk about ...
How do I write a Makefile?
The simplest way is to find one made by someone else and modify it .
Let's what kind of stuff you can find in a Makefile:
1) Macros
Macros are witten this way :
name = data
For example the macro
CC =gcc
SRC = main.c
CFLAGS= -g
The next line
$(CC) $(CFLAGS) $(SRC)
to be transformed and executes as :
gcc -g main.c
2) Comments
Any line beginning with a # is a comment and will be ignored.
3) Explicit rules
Explicit rules tell make which files depend on the compilation of other files,
and the commands to compile the file.
They look like this
targetfile : sourcefiles
commands
Insert TAB character before each command wich is kind of separator,
use a common text editor like mcedit or emacs , some text editor may get
in trouble with the tabs.
This rule says that in order to create the targetfile, make must perform
all those commands on sourcefiles. For example, the rule:
main: main.c my_header.h
gcc -o main main.c List.h
means that in order to create the target file main, the source files main.c
and my_header.h have to exist, and make should use the command:
gcc -o main main.c my_header.h
4) Implicit rules
Implicit rules will persuade make to use the suffixes on the files to determine
what command to perform.(Pretty smart this make ). This is very good to know
... because i kind forgot about theese rules more than once ( Puah lots of
headaches)
main.o: main.c my_header.h.h
will have this effect:
$(CC) $(CFLAGS) -c main.c my_header.h
Example :
# Macros
CC = gcc
CFLAGS = -g
LIBS = -lpthread
SRC=main.c url1.c imagini.c table.c
OBJ=main.o url1.o imagini.o table.o
# Explicit rule
all: $(OBJ)
$(CC) $(CFLAGS) -o main $(OBJ)
$(LIBS)
# Implicit rules
table.o: table.h table.c
url1.o: url1.h url1.c
imagini.o: imagini.h imagini.c
main.o: main.c
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